Transmitters used for communication devices such as mobile phones and wireless LANs are required to ensure the accuracies of radio signals regardless of the strengths of transmission powers and to operate with lower power consumption. In particular, since a power amplifier located at the most downstream stage of a transmitter consumes 50% or more of the entire power consumption of the transmitter, a power amplifier is required to have a high power efficiency.
In recent years, as a power amplifier that is expected to have a high power efficiency, a switching amplifier has gained attention. A switching amplifier inputs a pulse wave-form signal and amplifiers the power of the pulse wave-form signal while keeping the wave-form.
In a transmitter using a switching amplifier, a filter element satisfactorily suppresses other than a desired frequency component of the output signal of the switching amplifier. Thereafter, the resultant signal is emitted from an antenna.
FIG. 1 shows an ordinary example of the structure of a class-D amplifier that typifies a switching amplifier.
The class-D amplifier shown in FIG. 1 has two switch elements SW0 and SWG located in series between the power supply and the ground. Complementary pulse signals as open/close control signals are input to the two switch elements SW0 and SWG such that one of these switch elements becomes the ON state. When the switch element SW0 on the power supply side becomes the ON state and the switch element SWG on the ground side becomes the OFF state, the output voltage of the amplifier is the power supply voltage; otherwise, the output voltage of the amplifier is a ground potential.
Since a class-D amplifier does not require a bias current, the power loss is ideally 0. Switch elements can be composed of electric field transistors, bi-polar transistors, or the like.
FIG. 2 shows an ordinary example of the structure of a multi-level class-D amplifier that outputs a voltage in multiple levels.
The multi-level class-D amplifier shown in FIG. 2 has a plurality (N+1) of switch elements SW0, SW1, . . . , and SWN connected between a plurality (N+1) of power supplies and the output terminal. The plurality of switch elements SW0, SW1, . . . , and SWN are controlled so that only one of them becomes the ON state. The output voltage of the amplifier is the voltage of the power supply connected to a switch element that is the ON state. In other words, the multi-level class-D amplifier can output voltages corresponding to the number of power supplies.
Here, the structure of a transmitter using a class-D amplifier will be described.
For example, a W-CDMA (Wideband Code Division Multiple Access) transmitter generates a digital baseband (hereinafter referred to as DBB) signal and amplifiers it. The DBB signal is a multi-bit signal composed of 10 bits or more; however, the number of bits of a signal that can be input to the class-D amplifier is smaller than the number of bits of the DBB signal.
Thus, when the DBB signal is used for the class-D amplifier, the number of bits of the DBB signal is required to be decreased. Generally, if the low order bits are simply discarded, whenever one low order bit is discarded, the quantization noise increases by 6 dB. The delta-sigma modulator is a circuit technique that can decrease the number of bits without increasing the quantization noise in the band in the neighborhood of a desired frequency.
In the transmitter using the delta-sigma modulator, the modulator performs the delta-sigma modulation for a DBB signal, an amplitude signal generated based on the DBB signal, or the like. The number of bits of the output signal of the delta-sigma modulator is set to be the same number with the number of bits that can be input to the class-D amplifier located on the downstream side of the delta-sigma modulator.
FIG. 3 shows an ordinary example of the structure of the delta-sigma modulator (Non-Patent Literature 1, page 71).
The delta-sigma modulator shown in FIG. 3 has adders 131-1 and 131-2, delaying units 132-1 and 132-2, and quantizer 300. Delaying unit 132-1 and adder 131-2 compose an inner integrating unit.
Quantizer 300 quantizes the output signal of adder 131-2 with a predetermined number of bits.
Delaying unit 132-2 delays the output signal of quantizer 300 by one clock cycle.
Adder 131-1 calculates the difference between the input signal and the output signal of delaying unit 132-2.
Delaying unit 132-1 delays the output signal of adder 131-2 by one clock cycle.
Adder 131-2 calculates the sum of the output signal of adder 131-1 and the output signal of delaying unit 132-1.
If the input signal of the delta-sigma modulator is represented by U(z), the output signal thereof is represented by V(z), and the quantization noise that occurred in quantizer 300 is represented by E(z), the following formula can be obtained.[Formula 1]V(z)=U(z)+(1−z−1)·E(z)  (1)
The noise N(z) contained in the output signal V(z) can be expressed by the following formula.[Formula 2]N(z)=(1−z−1)·E(z)  (2)
where[Formula 3]z=exp(2πjf/fclk)  (3)
where f is the signal frequency of the radio signal; and fclk is the clock frequency of the delta-sigma modulator.
Thus, if the signal band that a desired radio signal occupies is represented by fB, the integrated noise in the signal band can be expressed by the following formula.[Formula 4]∫0fB|1−exp(−2πjf/fclk)|·|E(z)|·df  (4)
The W-CDMA technique requires 33 dB or greater of SNR (Signal-Noise Ratio) in the neighborhood of a desired signal band. To satisfy this requirement and to decrease the integrated noise expressed by formula (4), fclk is required to be increased; E(z) is required to be decreased.
Non-Patent Literature 2 discloses a delta-sigma modulator that operates at 4 GHz of fclk. To decrease E(z), quantizer 300 is required to quantize a signal with multiple bits. Although Non-Patent Literature 2 discloses the quantizer that quantizes a signal with one bit, if the number of bits of the quantizer is increased, the operation speed, that is to say, fclk will be decreased.